A memory cell typically is formed of a channel between two terminals, known as the source and drain. Above, the channel is some form of memory element, which is activated by a third terminal, known as the gate.
To create an array of memory cells, the gates of rows of cells are connected together in word lines, the drains of columns of cells are connected together as bit lines and the sources are connected together as either bit lines or common sources. The arrangement of word lines, bit lines and common lines or common sources is known as the architecture of the array and there are many such architectures.
Our common architecture is called the “NOR array”. Such an architecture is shown in FIG. 1, to which reference is now made.
FIG. 1 shows an array of cells 10 whose gates G are connected in rows by word lines WLi and whose drain D are connected in columns by bit lines BLj. The sources S of the cells are connected to ground lines, indicated by arrowheads. FIG. 1 indicates that the word lines WLi are connected to a row decoder (XDEC) 12 and the bit lines BLj are usually accessed by a multiplier (YMUX) 16 through which the cells can be biased and read. The NOR architecture of FIG. 1 is useful for read only memory (ROM) arrays and FLASH electrically erasable, programmable read only memory (EEPROM) arrays and is very common for floating gate type cells. Non-FLASH EEPROM arrays (i.e. arrays wherein each cell or a small subset of cells is individually erasable) require a modified NOR array, as shown in FIG. 2, to which reference is now made.
In this architecture, each cell 10 is controlled by a select cell 18 and a row of select cells 18 is controlled by a select line SELi. Select cells 18 are typically standard transistors (such as n-channel MOS transistors) whose drains are connected to the bit lines BLj, whose sources are connected to the drain of the cells 10 that they control and whose gates are connected to the relevant select line SELi. When a cell, such as cell 10A, is to be accessed, its word line WLi and associated select line SELi are activated as is its bit line BLj. Because select line SELi and word line WLi are activated, the cells of the ith row are potentially activated. However, the only cell that will be accessed is cell 10A since only its drain will receive power, through activated select transistor 18A. Other cells that share the accessed word line WLi and select line SELi do not feel any high voltage because their bit lines are not activated. Furthermore, cells sharing the same bit line BLj do not feel the high bit line voltage because their select transistors SELi are off.
In addition to the “per-cell select transistor”, there are typically “array select transistors”, which segment the array into blocks. The need for so many cell select transistors significantly increases the cell area.